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PROGRAMMABLE INFRARED REMOTE TRANSMITTER WITH BUILT-IN TRANSISTOR
DESCRIPTION
SC73P2602 is SC73 core based programmable remote
transmitter (4-bit MCU) with infrared transmitting transistor and built-in 2K OTP program memory supporting in-system program (ISP) which can optimize the stock control. Due to the infrared transmitting transistor embedded, few periphery components are needed and the cost is reduced. And the quick mask function that SC73P2602 supported can meet the mass production delivery requirements as soon as possible due to its mask cycle is 2~3 weeks less than the traditional mask cycle. SC73P2602 is available in several packages and pin to pin compatible with all the products of SC73C16 and SC73P16 series.
FEATURES
SC73 core. 2Kx9 bit OTP and 32x4 bit RAM Built-in infrared transmitting transistor: IOL = 350mA. Support external infrared transmitting transistor. Internal carrier generator. Internal power-on clear circuit (POC). Internal watchdog timer (WDT).
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3-level program stack. Support low voltages detect (LVD). Supports In-System Programming (ISP). Oscillator frequency: FOSC=4MHz (Typ.). System clock: FMAIN= FOSC /8. Instruction period: 5/ FMAIN. Operating voltage: 1.8V~3.6V, quiescent current is no higher than 1A.
BLOCK DIAGRAM
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ORDERING INFORMATION
Part No. SC73P2602SH1 SC73P2602SN1 SC73P2602SM2 SC73P2602SN2 SC73P2602RC2 SC73P2602RD2 SC73P2602SM3 SC73P2602SN3
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I/O 18 15 15 15 15 15 15 15 15 15 11 11 11 4 18 15 15 15 15 15 15 15 15 15 11
Package SOP-24-375-1.27 SOP-20-375-1.27 SOP-20-300-1.27 SOP-20-375-1.27 SSOP-20-225-0.65 SSOP-20-300-0.65 SOP-20-300-1.27 SOP-20-375-1.27 SSOP-20-225-0.65 SSOP-20-300-0.65 SOP-16-225-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SOP-8-225-1.27 SOP-24-375-1.27 SOP-20-375-1.27 SOP-20-300-1.27 SOP-20-375-1.27 SSOP-20-225-0.65 SSOP-20-300-0.65 SOP-20-300-1.27 SOP-20-375-1.27 SSOP-20-225-0.65 SSOP-20-300-0.65 SOP-16-225-1.27
Marking SC73P2602SH1 SC73P2602SN1 SC73P2602SM2 SC73P2602SN2 SC73P2602RC2 SC73P2602RD2 SC73P2602SM3 SC73P2602SN3 SC73P2602RC3 SC73P2602RD3 SC73P2602SC1 SC73P2602SC2 SC73P2602SC3 SC73P2602SA SC73P2602SH1 SC73P2602SN1 SC73P2602SM2 SC73P2602SN2 SC73P2602RC2 SC73P2602RD2 SC73P2602SM3 SC73P2602SN3 SC73P2602RC3 SC73P2602RD3 SC73P2602SC1
Material Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free Pb free
Packing type Tube Tube Tube Tube Tube Tube Tube Tube Tube Tube Tube Tube Tube Tube Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel
SC73P2602RC3 SC73P2602RD3 SC73P2602SC1 SC73P2602SC2 SC73P2602SC3 SC73P2602SA SC73P2602SH1TR SC73P2602SN1TR SC73P2602SM2TR SC73P2602SN2TR SC73P2602RC2TR SC73P2602RD2TR SC73P2602SM3TR SC73P2602SN3TR SC73P2602RC3TR SC73P2602RD3TR SC73P2602SC1TR
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Part No. SC73P2602SC2TR SC73P2602SC3TR SC73P2602SATR
I/O 11 11 4
Package SOP-16-225-1.27 SOP-16-225-1.27 SOP-8-225-1.27
Marking SC73P2602SC2 SC73P2602SC3 SC73P2602SA
Material Pb free Pb free Pb free
Packing type Tape & Reel Tape & Reel Tape & Reel
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Input Voltage Storage Temperature Operating Temperature Symbol VDD VI TSTG TOPR Value -0.3 ~ +4.0 -0.3 ~ VDD+0.3 -65 ~ +125 -20 ~ +70 Units V V C C
DC ELECTRICAL CHARACTERISTICS (unless otherwise specified, VDD=3V, Tamb=25C)
Characteristics Operating Voltage Low-Voltage Reset Low-Voltage Detect Symbol VDD VLVR VLVD Operating Operating Current IDD mode: FOSC=4MHz P53 IOH VOH=2.7V P02~P03 P1, P2, P3 P50~P52 P53 P53(N-MOS Output Low Current IOL VOL=0.3V open drain) P02~P03 P1, P2, P3 P50~P52 -5.5 -19 -350 mA 0.6 Test Conditions VDD=3.6V VDD=3.0V VDD=1.8V Min. 1.8 2 0.7VDD 0 Typ. 1.55 1.7 3.0 2.0 0.3 4 1.35 9.5 Max. 3.6 1 6 VDD 0.3VDD mA A MHz V V mA Units. V V V
Stop mode (oscillator is off) Oscillator Frequency Oscillator Voltage Input High Voltage Input Low Voltage
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FOSC VOSC VIH VIL
Output High Current
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Characteristics
Symbol
Test Conditions P00 VDD=3.6V P01~P03 P1, P2, P3 P50~P52 P00
Min. -
Typ. 50 150 100 220 600 650
Max. -
Units.
Pull-Up Resistor
RPU
VDD=3.0V
P01~P03 P1, P2, P3 P50~P52 P00 P01~P03 P1, P2, P3 P50~P52
k
VDD=1.8V
PIN CONFIGURATIONS
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PIN CONFIGURATIONS
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PIN DESCRIPTIONS
Pin No. -RC2 -SH1 -SN1 -RD2 -SM2 -SN2 24 1 2 3 6 7 8 9 10 11 12 13 14 15 16 17 18
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-RC3 -RD3 -SM3 -SN3 20 1 4 5 7 8 9 10 11 12 13 14 15 16 17 18 2 3 6 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 1 4 5 6 7 8 9 10 11 12 13 14 2 3 4 7 5 6 8 9 10 11 12 13 14 15 16 1 2 7 8 1 2 3 4 5 6 -SC1 -SC2 -SC3 -SA
Pin name
Pin type
Description
20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -
6 9 7 8 11 12 13 14 15 16 17 18 19 20 1 2 3 4 10
VDD GND OSC1 OSC2 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P50 P51 P52
PWR PWR I O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Power supply Ground External oscillator input port External oscillator output port Input port
I/O port
19
20 21 4 5
Remote signal output with carrier. Can be set as 23 19 5 19 15 15 3 P53 O push-pull output or big current opendrain output by program 22 NC NC
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PIN STRUCTURE
Pin name Pin type Pin structure Remark
P00~P01
I
Built-in pull-up resistor
Enter input mode after reset; P02~P03 P10~P13 P20~P23 P30~P33 P50~P52 I/O Pull-up resistor available in input mode; Push-pull output in output mode, and LED can be driven by low level.
High-impedance status after reset; Open-drain output for
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P53
O
using internal infrared LED driver transistor ; Push-pull output for using external infrared LED driver transistor.
FOSC OSC1 PAD
OSC1 OSC2
I O
OSC2 PAD Oscillator stop signal
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FUNCTION DESCRIPTION
1. Word width
Word width for SC73P2602 is 9-bit, that is 2K word is 2Kx9-bit. 2. Instruction period
Instruction and internal operation are both based on main clock. The instruction period is the time of executing a whole instruction. There are single-/double-period instructions available for SC73P2602. An instruction period consists of 5 beat which is a system clock period (1/FMAIN). Hence, an instruction period is 5/ FMAIN. 3. PC
PC for SC73P2602 is 11-bit and the maximum addressable memory is 2K. PC value is the address of next instruction to be executed and it is 0 after reset. In general, PC is added by 1 after executing an instruction because instructions for SC73P2602 is single-byte instruction. Fixed value is evaluated to PC when executing jump, subprogram call and subprogram return. 4. MBR
Memory buffer register (MBR) is the write-only, higher 5-bit of the program pointer. The ROM of SC73P1602 can be divided into 15 blocks and each block has 128 bytes. These blocks can be addressed by the MBR. For program jump, the BLOCK value containing the target address should be loaded to MBR before executing BSS addr7 instruction. 5. STACK
www..com register is used for storing PC when calling subprogram. 3-level subprogram can be called for there is 11-bit stack
only 3-level hardware stack registers in SC73P2602. 6. B, H, D
4-bit data look-up pointer registers. Lower 3-bit of register B and all bits (4-bit) of H, D are used as pointers pointing to data table when accessing constant data in OTP whose space of 2K can be used for data table or program memory, otherwise, register B, H, D act as general purpose register as others. Constant data stored in the table can be accessed through table look-up instruction. 7. ALU
The arithmetic and logic unit plays a leading role in performing various operations of 4-bit binaries. The operation of ALU will change the carry flag (CF) and the zero flag (ZF). 8. ACC
4-bit accumulator, it is mostly used to store data and results.
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9.
CF
Carry flag. 10. SF Status flag. jump instruction is only effective only when SF=1. SF is 1 after reset. 11. CH0, CH1, CL0, CL1 CH0, CH1, CL0 and CL1 are carrier level control registers for controlling the high and low level to (CH+1)/Fosc and(CL+1)/Fosc. Where, Fosc is oscillator frequency, CH0 and CH1 are higher 4-bit and lower 4-bit of CH respectively, while CL0 and CL1 are higher 4-bit and lower 4-bit of CL. 12. LL, LH 4-bit LL register, lower 4-bit of RAM addressing pointer, can be used as general register as well. 4-bit LH register, LH[0] is the MSB of RAM addressing pointer.
Note: LH[3] is LVD flag and it is "0" when VDD< VLVD, otherwise it is "1". Typical application: this bit is used for judging whether the circuit is working in low-voltage area to avoid incomplete code transmission. Typical value for is VLVD 1.7V. 13. PR (PR, PR2)
www..com The port mode register, which specifies the input mode or output mode of the I/O port, is 4-bit write-only. When
PR=1, the corresponding port is set to output mode. PR=0, it is set to input mode. The execution of the HOLD instruction won't affect the I/O modes of operation. When reset, PR=0. The port is in input mode.
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14. TM 4-bit function register with different functions for write TM and read TM. Write TM: 17-bit timer run enable, P53 structure select and carrier generator enable; Read TM: the 12th~15th bit value of 17-bit timer (the lowest bit is the first bit)
15. OTP address assignment OTP ROM for SC73P2602 is 2K (9-bit), and the address assignment is shown below: Address 0000H ~ 003FH
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Description Subprogram entry address (can be multiplexed as normal program area ) Program area (can be multiplexed as data table)
0040H ~ 07FFH
16. RAM Data memory consists of 32x4 bits and is used to store temporary data and results after a program is executed. It can address the entire RAM areas by r LH[0] and LL[3:0]. When reset, the contents of RAM are not defined. It is recommend to initialize it at the beginning of program. 17. TIMER SC73P2602 has one 17-bit timer whose operating frequency is FCFMAIN.
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Reset value for timer is 1FFFFH, and it counts down.
th WDT overflow reset signal is generated if the 17 bit of timer is converted from "1" to "0".
Timer is reset if system is reset (including power-up reset, low-voltage reset and WDT overflow reset), HOLD is cleared or reset instruction TMRST is executed.
th Program is only executed when the 12 bit of time is converted from "1" to "0" after HOLD cleared.
18. Carrier generator Various carrier with different duty factors and frequencies are generated through setting high/low level duration by carrier register (see CH0, CH1, CL0, CL1 description). 19. I/O port SC73P2602 has 5 groups (20 in all) of I/O ports and most have both input/output modes (except P00 and P01 can only be used as input and P53 can only be used as output), details are as follows: P00-P01: input pin with pull-up resistor. It can be used for keyboard scan input and input low level can clear HOLD status; P02-P03: input/output port. The input/output characteristic is decided by PR. When used as input port, it has pullup resistor and can be used as keyboard scan input, input low level can clear HOLD status; when used as output pin, it can be used for keyboard scan output and output low level can drive LED directly. P10-P13: same as P02; P20-P23: same as P02; P30-P33: same as P02; P50-P52: same as P02; P53: output infrared remote signal with carrier. There are two structures: push-pull structure is for external infrared emitter driving and big current open-drain structure is for driving infrared emitter directly, with opposite pole of the former structure.
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20. Low voltage detect (LVD)
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Note: 1. 2. 3. 4. 5. When VDDVOSC, oscillation start up. When VDD>VLVD, LH[3] = "1"; when VDDHANGZHOU SILAN MICROELECTRONICS CO.,LTD
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INSTRUCTION SET
Symbol addr7 b C vect Z #k %p PUSH POP TIMER 1. Transmit instruction Instruction LD A, LL LD A, B LD A, H LD A, D LD A, @LL LD A, #k LD CL1, A LD CL0, A
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lower 7-bit of address Bit address (0~3) carry flag Subprogram entry address vector Zero flag: when ACC=0, Z=" 1"; ACC0, Z="0" immediate data(0~15) port address evaluate the right value to left Push pop 17-bit timer
Operation A LL AB AH AD A RAM(LL) Ak CL1 A CL0 A CH1 A CH0 A A ROM(BD)7-4 A ROM(BD)3-0 A ROM(BD)8 RAM(LL) ROM(BD)7-4 RAM(LL) ROM(BD)3-0 RAM(LL) ROM(BD)8 LL A LL k RAM(LL) A RAM(LL) k DA HA BA PR A
Flag CF SF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
cycle 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2 2 2
LD CH1, A LD CH0, A LDH A, @BD LDL A, @BD LDS A, @BD LDH @LL, @BD LDL @LL, @BD LDS @LL, @BD LD LL, A LD LL, #k LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD PR, A
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Instruction LD PR2, A LD TM, A LD A,TM 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15 16. 17. 18.
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Operation PR2 A TM A A TM
Flag CF SF 1 1 1
cycle 2 2 2
LD A, LL LD A, B LD A, H LD A, D LD A, @LL LD A, #k LD CL1, A LD CL0, A LD CH1, A LD CH0, A LDH A, @BD LDL A, @BD LDS A, @BD LDH @LL, @BD LDL @LL, @BD LDS @LL, @BD LD LL, A LD LH, A LD LL, #k LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD PR, A LD PR2, A LD TM, A LD A,TM
Load values in the LL register to the accumulator. Load values in the BR register to the accumulator. Load values in the HR register to the accumulator. Load values in the DC register to the accumulator. Load the contents of RAM pointed at by the LL register to accumulator. Load the 4 bit immediate K to accumulator. Load the content of the accumulator to the CL1 register. Load the content of the accumulator to the CL0 register. Load the content of the accumulator to the CH1 register. Load the content of the accumulator to the CH0 register. Load the higher 4 bit of ROM data pointed at by the BHD to accumulator. Load the lower 4 bit of ROM data pointed at by the BHD to accumulator. Load the MSB of ROM data pointed at by the BHD to accumulator Load the higher 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the lower 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the MSB of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the contents of the accumulator to the LL register. Load the contents of the accumulator to the LH register. Load immediate K to the LL register. Load the content of the accumulator to the RAM pointed at by the LL register. Load the immediate K to RAM pointed at by the LL register. Load the content of the accumulator to the DC register. Load the content of the accumulator to the HR register. Load the content of the accumulator to the BR register. Load the content of the accumulator to the port register(PR). Load the content of the accumulator to the port register(PR2). Load the content of the accumulator to the timer register. Load the content of the timer register to the accumulator.
19.
20. 21. 22. 23. 24. 25. 26. 27. 28.
Note: executing transmit instructions above will not change CF and SF remains 1.
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2.
Input/output instructions Instruction LD A, %p LD @LL, %p LD %p, A LD %p, @LL 01. 02. 03. 04. LD A, %p LD @LL, %p LD %p, A LD %p, @LL Operation A PORT(p) @LL PORT(p) PORT(p) A PORT(p) @LL Flag CF SF /Z /Z 1 1 Cycle 2 2 2 2
Load the value of port(P) to the accumulator Load the value of port(P) to RAM pointed at by the LL register. Load the contents of the accumulator to port (P). Load the contents of RAM pointed at by the LL register to port(P).
Note: The above four input/output instructions are used mostly for port operation, and the two read instructions will affect the status flag SF. 3. Arithmetic and logic instructions Instruction ADD A, @LL ADDC A, @LL ADD A, #k ADD LL, #k SUBRC A, @LL INC @LL DEC @LL
www..comLL INC
Operation A A+RAM(LL) A A+RAM(LL)+CF A A+k LL LL+k A RAM(LL)-A-/CF RAM(LL) RAM(LL)+1 RAM(LL) RAM(LL)-1 LL LL+1 LL LL-1 D D+1 H H+1 B B+1 D D-1 H H-1 B B-1 A A&RAM(LL) A A | RAM(LL) A A^RAM(LL)
Flag CF C C SF /C /C /C /C C /C C /C C /C /C /C C C C /Z /Z /Z
Cycle 1 1 1 2 1 1 1 2 2 2 2 2 2 2 2 1 1 1
DEC LL INC D INC H INC B DEC D DEC H DEC B AND A, @LL OR A, @LL XOR A, @LL
01. 02.
ADD A, @LL ADDC A, @LL
Add the contents of RAM pointed at by the LL to accumulator, and store the sum in the ACC. This operation will affect SF, SF=/C. Add the contents of RAM pointed at by the LL register to accumulator with carry. Store the carry bit in the CF. This operation will affect SF, SF=/C.
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03. 04.
ADD A, #k ADD LL, #k
Add immediate K to accumulator. And store the sum in the ACC. This will affect SF, SF=/C. Add immediate K to the LL register and store the sum in the LL. This will affect SF, SF=/C. Subtract instruction with borrow (the complement of carry). Subtract the contents of the accumulator from the contents of RAM pointed at by the LL
05.
SUBRC A, @LL
register, subtract the complement of the carry bit, then store the results in the accumulator, transfer the carry bit to the CF, this will affect SF and CF, SF=C. Increment instruction. Increment the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=/C. Decrement instruction. Decrement the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=C. Increment instruction. Increment the contents of the LL register by 1. This will affect SF, SF=/C. Subtract 1 from the content in register LL. SF is affected, SF=C. Increment instruction. Increment the contents of the DC register by 1. This will affect SF, SF=/C. Increment instruction. Increment the contents of the HR register by 1. This will affect SF, SF=/C. Increment instruction. Increment the contents of the BR register by 1. This will affect SF, SF=/C. Decrement instruction. Decrement the contents of the DC register by 1. This will affect SF, SF=C. Decrement instruction. Decrement the contents of the HR register by 1. This will affect SF, SF=C. Decrement instruction. Decrement the contents of the BR register by 1. This will affect SF, SF=C. The contents of the accumulator and RAM pointed at by the LL register are ANDed and the results are stored in the accumulator. SF is changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are ORed and the results are stored in the accumulator. SF is changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are XORed and the results are stored in the accumulator. SF is changed, SF=/Z.
06. 07. 08. 09 10. 11. 12. 13. 14. 15. 16. 17. 18.
INC @LL DEC @LL INC LL DEC LL INC D INC H INC B DEC D DEC H DEC B AND A, @LL OR A, @LL XOR A,@LL
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4.
Bit operation instructions Instruction CLR @LL, b SET @LL, b TEST @LL, b Operation RAM(LL)b0 RAM(LL)b1 SF/RAM(LL)b Flag CF SF 1 1 * Cycle 2 2 2
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01. 02. 03.
CLR @LL, b SET @LL, b TEST @LL, b
Clear the B-bit of the RAM pointed at by the LL register. Set the B-bit of the RAM pointed at by the LL register to 1. Test the B-bit of the RAM pointed at by the LL register. If this bit is1, the SF is set to 0; otherwise, the SF is set to 1.
5.
Carry operation instructions Instruction CLR CF SET CF TESTP CF 01. 02. 03. CLR CF SET CF TESTP CF CF0 CF1 SFCF Clear the carry flag to 0. Set the carry flag to 1. Test the carry flag, send the carry flag to SF. Operation Flag CF 0 1 SF 1 1 CF Cycle 2 2 1
6.
Jump instructions Instruction BSS addr7 01. BSS addr7 Operation PC[6:0] addr7 Flag CF SF 1 Cycle 2
Jump to addr7, jump range: in the block (128-byte)
7.
Subroutine instructions Instructions Operation PUSH(PC+1); PC vect POP(PC) CALLS vect RET Flag CF SF Cycle 2 2
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CALLS vect RET 01. 02. 8.
Call the subroutine, and the subroutine address can only be 000H-01FH. Subroutine back
Other instructions Instructions HOLD NOP TMRST TIMER 1FFFFH Operation Flag CF SF 1 Cycle 1 1 1
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01. 02. 03.
HOLD NOP TMRST
MCU enters power-saving mode with little power dissipation after executing this instruction. Nop instruction, this instruction has no effect. Timer reset. Set all bits of timer to 1. this instruction is usually used for reset watchdog.
MACRO INSTRUCTIONS
symbol: addr7 1. JMPS Format JMPS address Function Jump in ROM Expression Address is the absolute address, it can be a digital, symbol defined by EQU or the address symbol. Combined by: LD MBR, #k BSS addr7 Example JMPS MAIN JMPS 100H 2. VENT Format
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lower 7-bit of program address
;address=k*128+addr7
VENT address Define the entry address of sub-program and main program.
Function Expression Address is the absolute address, it can be a digital, symbol defined by EQU or the address symbol. Combined by: Same as JMPS addr11, it is combined by: LD MBR, #k BSS addr7 ;address=k*128+addr7
This instruction should be included and must be at the beginning of the program. The first VENT denotes the main program address and the following VENT instructions denote the entry of the sub-program. In general, 15 sub-programs can be defined at most. All the sub-programs called by CALL instruction should be defined in VENT, or else errors will occur in assembly. Example VENT MAIN VENT SUB1 VENT SUB2 ......
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ORG 100H MAIN: NOP NOP CALLS SUB1 CALLS SUB2 ...... SUB1: ...... SUB2: ......
;pseudo instruction for redefining address of following instructions
PSEUDO INSTRUCTIONS
1. ORG Format ORG address Function Redefine following start address Expression Address: redefined address, can be binary, decimal or hexadecimal. Redefined address is an absolute address and should be higher than that above, or a fault is occurred during compiling. 0000H is defaulted if no address is set by ORG instruction. Example ORG 0100H 2. EQU
Format www..com Symbol EQU digital Function Define a digital as a symbol. Symbol digital. Expression Symbol should be legal (begin as a letter and composed by letters, digital and underline), and digital should be binary, decimal or hexadecimal. There is no colone before EQU in definition, and it can only be used after the definition. Example Data1 EQU 12H Data2 EQU 1001B 3. DB Format [Num] DB data Function Define data with number of num.
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Expression Num: indicates number of data, default value is 1. Data: data to be written to ROM. lower 9-bit value of data is taken without warning if data is larger than 1FFH because ROM is only 9-bit. Example DB 12H DB 10010B 12H DB 55H 4. END Format END Function Indicates the ending Expression Content after END will not be processed by assembler. If END is omitted, the assembler will process all the lines of the source file. Example END ; fill in one data ; fill in one data ; fill in 18 data
REMOTE CONTROL FLOW CHART
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2009.11.19 Page 20 of 28
TYPICAL APPLICATION CIRCUIT1 ---(56 Keys)
VDD 0.1F 47F
VDD IRD 270 2
1 2 3 33pF 4 4MHz 5 33pF 6 7 8 9
GND P50 P51 XT1 XT2 P52 P00 P01 P02
VDD 20 P53 19 P33 18 P32 17 P31 16 P30 15 P23 14 P22 13 P21 12 P20 11
K08 K07 K06 K05 K04 K03 K02 K01
K16 K15 K14 K13 K12 K11 K10 K09
K24 K23 K22 K21 K20 K19 K18 K17
K32 K31 K30 K29 K28 K27 K26 K25
K40 K39 K38 K37 K36 K35 K34 K33
K48 K47 K46 K45 K44 K43 K42 K41
K56 K55 K54 K53 K52 K51 K50 K49
SC73P2602SN3
10 P03
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The capacitor between VDD and GND should be close to IC and the routing should be as short as possible.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 21 of 28
TYPICAL APPLICATION CIRCUIT2 ---( 56 Keys with built in TR)
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The capacitor between VDD and GND should be close to IC and the routing should be as short as possible.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 22 of 28
TYPICAL APPLICATION CIRCUIT3 ---(36 Keys with built in TR)
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The capacitor between VDD and GND should be close to IC and the routing should be as short as possible.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 23 of 28
PCB WIRE LAYOUT SCHEMATIC:
Transmitting tube output ground line
The transmitting tube ground line and IC ground line should layout separated or overstriking ground line.
The above IC only use to hint, not to specified. Note: * In wire layout, the power filter capacitor should be close to IC. * In wire layout, should avoid power line and ground line too long. * Recommended infrared transmit unit and IC ground line should layout separated, or overstriking lines. * The emitter of triode connect 2 resistor at least.
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* Recommended triode use 8050. touches the remote controller without crust in testing.
* IC oscillator input mustn't be on the outside layer, thus to avoid the abnormal working when human body
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 24 of 28
PACKAGE OUTLINE
SSOP-20-225-0.65 Unit: mm
6.500.20 20 11
6.400.20
1
10 1.200.05 08 +0.10 -0.05 +0.08 0.127 -0.04
1.45MAX
4.400.10
0.65
0.25
SSOP-20-300-0.65
+0.20 0.80 -0.25
0.10
0.600.15
Unit: mm
08
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7.800.20
5.250.20
0.30
0.65
+0.10 0.15 -0.06 1.85MAX
7.200.20
1.500.20 0.150.10
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
7.620.20
REV:1.1
2009.11.19 Page 25 of 28
PACKAGE OUTLINE (Continued)
SOP-8-225-1.27
0.42
Unit: mm
0.200.05 1.27
5.00.3
0.150.10
SOP-16-225-1.27
Unit: mm
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HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 26 of 28
PACKAGE OUTLINE (Continued)
SOP-20-300-1.27 Unit: mm
0.200.10 1.27 0.45
12.700.25
SOP-20-375-1.27
Unit: mm
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HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.1
2009.11.19 Page 27 of 28
PACKAGE OUTLINE (Continued)
SOP-24-375-1.27 Unit: mm
9.810.61
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MOS DEVICES OPERATE NOTES:
Electrostatic charges may exist in many things. Please take following preventive measures to prevent effectively the MOS electric circuit as a result of the damage which is caused by discharge: The operator must put on wrist strap which should be earthed to against electrostatic. Equipment cases should be earthed. All tools used during assembly, including soldering tools and solder baths, must be earthed. MOS devices should be packed in antistatic/conductive containers for transportation.
Disclaimer : * Silan reserves the right to make changes to the information herein for the improvement of the design and performance without further notice! Customers should obtain the latest relevant information before placing orders and should verify that such information is complete and current. * All semiconductor products malfunction or fail with some probability under special conditions. When using Silan products in system design or complete machine manufacturing, it is the responsibility of the buyer to comply with the safety standards strictly and take essential measures to avoid situations in which a malfunction or failure of such Silan products could cause loss of body injury or damage to property. * Silan will supply the best possible product for customers!
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
0.050.30
2.80MAX
7.60.3
REV:1.1
2009.11.19 Page 28 of 28

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